A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks
- Medus, L.D.
- Iakymchuk, T.
- Frances-Villora, J.V.
- Bataller-Mompean, M.
- Rosado-Munoz, A.
Revue:
IEEE Access
ISSN: 2169-3536
Année de publication: 2019
Volumen: 7
Pages: 76084-76103
Type: Article