A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

1. Medus, L.D.
2. Iakymchuk, T.
3. Frances-Villora, J.V.
4. Bataller-Mompean, M.
5. Rosado-Munoz, A.

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DOI: 10.1109/ACCESS.2019.2920885 GOOGLE SCHOLAR lock_openOpen access editor

Data source: Scopus