A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

  1. Medus, L.D.
  2. Iakymchuk, T.
  3. Frances-Villora, J.V.
  4. Bataller-Mompean, M.
  5. Rosado-Munoz, A.
Aldizkaria:
IEEE Access

ISSN: 2169-3536

Argitalpen urtea: 2019

Alea: 7

Orrialdeak: 76084-76103

Mota: Artikulua

DOI: 10.1109/ACCESS.2019.2920885 GOOGLE SCHOLAR lock_openSarbide irekia editor
Datuen iturria: Scopus